Dr.-Ing. Matthias Stecher, Founder

Device Physics

Sales & Marketing

2009 : Co-founder of the High Power Pulse Instruments GmbH
Since 2005 : Technical consultant for smart power technology developments
1998 – 2005 : Technology project manager for smart power technologies in Munich (Germany) for Infineon Technologies
1994 – 1998 : R&D engineer in the area of smart power technology development at the EZM Villach (Austria) of the SIEMENS AG
1995 : PhD degree of the RWTH Aachen (Germany) with the subject “coupled process-/device simulation”
1988 – 1994 : Research assistant at the RWTH Aachen (Germany) with the focus on software development for process, device and circuit simulation

List of Publications

BCD technologies in general

J. Busch, M. Denison, G. Groos, H. Gruber, R. Hofmann, N. Jensen, A. Meiser, P. Nelle, R. Weeger, W. Schwetlick, M. Stecher: “Key Features of a Smart Power Technology for Automotive Applications”; International Conference on Integrated Power Systems, 2002

Stecher, M.; Jensen, N.; Denison, M.; Rudolf, R.; Strzalkoswi, B.; Muenzer, M.N.; Lorenz, L.; “Key technologies for system-integration in the automotive and Industrial Applications”, Power Electronics, IEEE Transactions on; Volume 20, Issue 3, May 2005 Page(s):537 – 549

Denison, M.; Pfost, M.; Stecher, M.; Silber, D.; “Analysis and modeling of DMOS FBSOA limited by n-p-n leakage diffusion current”; Power Semiconductor Devices and ICs, 2005. Proceedings. ISPSD ’05. The 17th International Symposium on; 23-26 May 2005 Page(s):331 – 334

Denison, M.; Pfost, M.; Pieper, K.-W.; Markl, S.; Metzner, D.; Stecher, M.; “Influence of inhomogeneous current distribution on the thermal SOA of integrated DMOS transistors”; Power Semiconductor Devices and ICs, 2004. Proceedings. ISPSD ’04. The 16th International Symposium on; 24-27 May 2004 Page(s):409 – 412

Simulation & Modeling

Stecher, M.; Meinerzhagen, B.; Krücken, J.M.J.; Engl, W.L.; “A Modular Approach to Parallel Mixed Level Device/Circuit Simulation”, VLSI Process and Device Modeling, 1990. (1990 VPAD) 1990 International Workshop on;

Stecher, M.; Meinerzhagen, B.; Bork, I.; Krücken, J.M.J.; Maas, P.; Engl, W.L.; “Influence Of Energy Transport Related Effects On NPN BJT Device Performance And ECL Gate Delay Analyzed By 2D Parallel Mixed Level Device/circuit Simulation”; VLSI Process and Device Modeling, 1993. (1993 VPAD) 1993 International Workshop on; May 14-15, 1993 Page(s):170 – 171

Stecher, M.; Meinerzhagen, B.; Maas, P.; Engl, W.L.; “On the Influence of Thermal Diffusion and Heat Fluy on Bipolar Device and Circuit Performance”; Simulation of Semiconductor Devices and Processes, SISDEP 1993

Stecher, M.; Engl, W.L.; “KYOKO: a new approach to couple 2D process and device simulation”; Numerical Modeling of Processes and Devices for Integrated Circuits, 1994. NUPAD V., International Workshop on; 5-6 June 1994 Page(s):85 – 8

Reggiani, S.; Gnani, E.; Rudan, M.; Baccarani, G.; Corvasce, C.; Barlini, D.; Ciappa, M.; Fichtner, W.; Denison, M.; Jensen, N.; Groos, G.; Stecher, M.; “Experimental extraction of the electron impact-ionization coefficient at large operating temperatures”; Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 13-15 Dec. 2004 Page(s):407 – 410

Einfeld, J.; Schaper, U.; Kollmer, U.; Nelle, P.; Englisch, J.; Stecher, M.; “A new test circuit for the matching characterization of npn bipolar transistors”; Microelectronic Test Structures, 2004. Proceedings. ICMTS ’04. The International Conference on; 22-25 March 2004 Page(s):127 – 131

Rudan, M.; Reggiani, S.; Gnani, E.; Baccarani, G.; Corvasce, C.; Barlini, D.; Ciappa, M.; Fichtner, W.; Denison, M.; Jensen, N.; Groos, G.; Stecher, M.; “Theory and experimental validation of a new analytical model for the position-dependent Hall Voltage in devices with arbitrary aspect ratio”; IEEE Transactions on Electronic Devices, Vol 53, 2006

Rudan, M.; Reggiani, S.; Gnani, E.; Baccarani, G.; corvasce, C.; Ciappa, M.; Stecher, M.; Pogany, D.; Gornik, E.; “Physical models for smart-power devices”; Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference; 22-24 June 2006 Page(s):28 – 33

Rudan, M.; Reggiani, S.; Gnani, E.; Baccarani, G.; Corvasce, C.; Barlini, D.; Ciappa, M.; Fichtner, W.; Denison, M.; Jensen, N.; Groos, G.; Stecher, M.; “Experimental validation of a new analytical model for the position-dependent Hall voltage in semiconductor devices” ; Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European; 12-16 Sept. 2005 Page(s):565 – 568

ESD topic

D. Pogany, N. Seliger, M. Litzenberger, H. Gossner, M. Stecher, T. Müller-Lynch, W. Werner and E. Gornik, “Damage analysis in smart power technology electrostatic discharge (ESD) protection devices”, Microel. Reliab., Vol. 39 (1999), pp. 1143-1148. (special issue from Conf. ESREF’99, Bordeaux, France, 5-8 October 1999)

C. Fürböck, M. Litzenberger, D.Pogany, E.Gornik, N.Seliger, T.Müller-Lynch, M.Stecher, H.Gossner,W.Werner, “Laser interferometric method for ns-time scale thermal mapping of smart power ESD protection devices during ESD stress”, Microel. Reliab., Vol. 39 (1999), pp. 925-930. (special issue from Conf. ESREF’99, Bordeaux, France, 5-8 October 1999)

C. Fürböck, D. Pogany, M. Litzenberger, E. Gornik, N. Seliger, H. Gossner, T. Müller-Lynch, M. Stecher, W. Werner, “Interferometric temperature mapping during ESD stress and failure analysis of smart power technology ESD protection devices”, J. Electrostatics, vol. 49 (3-4), pp. 195-213 (2000)

C. Fürböck, K. Esmark, M. Litzenberger, D. Pogany, G. Groos, R. Zelsacher, M. Stecher, and E. Gornik, “Thermal and free carrier concentration mapping during ESD event in smart power ESD protection devices using an improved laser interferometric technique”, Microel. Reliab, Vol. 40 (8-10), pp.1365-1370 (2000) (special issue from ESREF’2000 Conference)

S. Bychikhin, M. Litzenberger, R. Pichler, D. Pogany, E. Gornik, G. Groos and M. Stecher, ”Thermal and free carrier laser interferometric mapping and failure analysis an “anti”-serially connected npn transistor ESD protection structures of smart power technology”, ESREF 2001, 1.-5.Oct. 2001, Bordeaux, France, Microel. Reliab. 41 (2001) pp.1501-1506.

D. Pogany, S. Bychikhin, M. Litzenberger, E. Gornik, G. Groos and M. Stecher, “Extraction of spatio-temporal distribution of power dissipation in semiconductor devices using nanosecond interferometric mapping technique”, Appl. Phys. Lett, vol. 81, no.15, pp.2881-2883, (2002).

D. Pogany, V. Dubec, S. Bychikhin, C. Fürböck, M. Litzenberger, G. Groos, M. Stecher, E. Gornik, “Single-shot thermal energy mapping of semiconductor devices with the nanosecond resolution using holographic interferometry”, IEEE Electron. Dev. Lett., vol. 23, no. 10, pp.606-608, (2002).

D. Pogany S. Bychikhin, C. Fürböck, M. Litzenberger, E. Gornik, G. Groos, K. Esmark, M. Stecher, “Quantitative internal thermal energy mapping of semiconductor devices under short current stress using backside laser interferometry”, IEEE Trans. Electron Dev., vol. 49, no.11, pp.2070-2079, (2002).

M. Blaho, D. Pogany, E. Gornik, M. Denison, G. Groos, M. Stecher; “Study of internal behavior in a vertical DMOS transistor under short high current stress by an interferometric mapping method”; Microel. Rel. 43 (2003), 545-548

D. Pogany, V. Dubec, S. Bychikhin, C. Fürböck, M. Litzenberger, S. Naumov, G. Groos, M. Stecher, E. Gornik, “Single-shot nanosecond thermal imaging of semiconductor devices using absorption measurements”, IEEE Trans. Dev. Mat. Reliab., vol. 3 (3), 2003, p. 85-88.

D. Pogany , S. Bychikhin, J. Kuzmik , V. Dubec , N. Jensen , M. Denison, G. Groos, M. Stecher and E. Gornik, “Thermal distribution during destructive pulses in ESD protection devices using a single-shot, two-dimensional interferometric method”, IEEE Trans. Dev. Mat. Reliab. Vol. 3, 2003, pp.197-201.

M. Denison, M. Blaho, P. Rodin, V. Dubec, D. Pogany, D. Silber, E. Gornik, M. Stecher: “Moving current filaments in integrated DMOS transistors under short duration current stress”, IEEE Trans. Electron Dev., vol.51, no.10, 2004, p.1695.

V. Dubec, S. Bychikhin, M. Blaho, M. Heer, D. Pogany, E. Gornik, M. Denison, N. Jensen, M. Stecher, G. Groos, “Multiple-time-instant 2D thermal mapping during a single ESD event”, Microel. Reliab., vol. 44, 2004. pp.1793-1798, Presented at ESREF04, Zurich, Switzerland, 4-8 October 2004

D. Pogany, S. Bychikhin, M. Denison, P. Rodin, N. Jensen, G. Groos, M. Stecher, E. Gornik, “Thermally-driven motion of current filaments in ESD protection devices”, Solid. St. Electronics, 2005, vol.49, no.3, 2005, 421-429.

M. Heer, V. Dubec, M. Blaho, S. Bychikhin, D. Pogany, E. Gornik, M. Denison, M. Stecher, G. Groos, “Automated setup for thermal imaging and electrical degradation study of power DMOS devices” Microel. Reliab., vol. 45 (2005), p.188-1693. (ESREF’2005)

S. Reggiani, E. Gnani, M. Rudan, G. Baccarani, S. Bychikhin, J. Kuzmik, D. Pogany, E. Gornik, M. Denison, N. Jensen, G. Groos, M. Stecher; “A new numerical and experimental analysis tool for ESD devices by means of the transient interferometric technique”, IEEE Electron Dev. Lett. 2005, vol. 26, no.12 (2005), p.916-918.

C.Fürböck, N.Seliger, D.Pogany, M.Litzenberger, E.Gornik, M.Stecher, H.Gossner, W.Werner, “Backside laserprober characterization of thermal effects during high current stress in smart power ESD protection devices”, Int. Electron Dev. Meeting (IEDM) Techn. Digest , San Francisco, USA (1998) pp.691-694.

C. Fürböck, M.Litzenberger, D.Pogany, E.Gornik, T. Müller-Lynch, H. Gossner , M. Stecher, W. Werner, “Study of bipolar transistor action during ESD stress in smart power ESD protection devices using interferometric temperature mapping”, Proc. ESSDERC’99, Leuven, Belgium 11-13. Sept. 1999, pp. 596-599.

C. Fürböck, D. Pogany, M. Litzenberger, E. Gornik, N. Seliger, H. Gossner, T. Müller-Lynch, M. Stecher, W. Werner, “Interferometric temperature mapping during ESD stress and failure analysis of smart power technology ESD protection devices”, Proc. EOS/ESD Symp., 26-30 Sept.1999, pp. 241-250.

K. Esmark, C. Fürböck, H. Gossner, G. Groos, M. Litzenberger, D. Pogany, R. Zelsacher, M. Stecher, and E. Gornik, “Simulation and experimental study of temperature distribution during ESD stress in smart-power technology ESD protection devices”, Proc. Int. Reliab. Phys. Symp. (IRPS’2000), San Jose, California, April 10-13, 2000. p.304-309

D. Pogany, C. Fürböck, M. Litzenberger, G. Groos, K. Esmark, P. Kamvar, H. Gossner, M. Stecher and E. Gornik, “Study of trigger instabilities in smart power technology ESD protection devices using a laser interferometric thermal mapping technique”, in Proc. EOS/ESD Symposium, Sept 9-13, Portland, USA, pp.216-227.2001

S. Bychikhin, M. Litzenberger, P. Kamvar, C. Fürböck, D. Pogany and E. Gornik G. Groos and M. Stecher, “Laser Interferometric Mapping of Smart Power ESD Protection Devices with Different Blocking Capabilities”, in Proc. ESSDERC 2001, Sept. 11.-13. 2001, Nuremberg, Germany, pp.231-234.

M. Litzenberger, C. Fürböck, D.Pogany, E. Gornik, K. Esmark, G. Groos, H. Gossner, M. Stecher: “Study of trigger homogeneity in ESD protection devices using backside laser interferometry”, Proc. ITE’2001, Informationstagung Mikroelektronik, 2001, Vienna, ISBN 3-85133-022-6, Österreichische Verband für Elektotechnik, p. 265-270.

M. Litzenberger, C. Fürböck, R. Pichler, S. Bychikhin, D. Pogany, E. Gornik, K. Esmark, G. Groos, H. Gossner, M. Stecher, “Laser-interferometric investigation of triggering behavior in CMOS and smart power ESD protection structures”, Proc. GME2001 Forum, Vienna, 2001, Ed. K. Riedling, ISBN:3-901578-07-2, pp. 129-132.

M. Blaho, D. Pogany, E. Gornik, M. Denison, G. Groos, M. Stecher; “Investigation of the internal behavior of a vertical DMOS transistor under short duration, high current stress by an optical thermal mapping method”; Proc. 6th Int. seminar on power semiconductors (ISPS), Prague 2002, pp. 63-67 (2002).

D. Pogany, M. Litzenberger, S. Bychikhin, E. Gornik, G. Groos, M. Stecher,”A method for extraction of power dissipating sources from interferometric thermal mapping measurements”, Proc. ESSDERC’2002, 24-26Sept. 2002, Florence, Italy, pp.243-246

D. Pogany , S. Bychikhin, J. Kuzmik , V. Dubec , N. Jensen , M. Denison, G. Groos, M. Stecher and E. Gornik, “Thermal distribution during destructive pulses in ESD protection devices using a single-shot, two-dimensional interferometric method”, IEDM 2002 Techn. Digest, San Francisco, USA 2002, pp. 345-348

D. Pogany, S. Bychikhin, E. Gornik, M. Denison, N. Jensen, G. Groos and M. Stecher: “Moving current filaments in ESD protection devices and their relation to electrical characteristics”, Proc. International reliability physics symposium (IRPS 2003), Dallas, USA, 30.9-3.4.2003, pp. 241-248

M. Denison, M. Blaho, D. Silber, J. Joos, M. Stecher, V. Dubec, D. Pogany, E. Gornik: “Hot Spot Dynamics in Quasi Vertical DMOS under ESD Stress”, Proc. 15th International Symposium on Power Semiconductor Devices & ICs (ISPSD’03), Cambridge, England, 14-17.4.2003, pp. 80-83.

D. Pogany, S. Bychikhin, C. Pflügl, V. Dubec, J. Kuzmik, M. Blaho, M. Litzenberger, G. Strasser, E. Gornik, “Thermal mapping of semiconductor devices with nanosecond resolution”, invited speaker on Workshop (Advanced RF characterization techniques) on European Microwave week 2003, GAAS conference, Munich Germany, 8 October 2003, pp. 105-131.

N. Jensen, G. Groos, M. Denison, J. Kuzmik, D. Pogany, E. Gornik, M. Stecher, “Coupled bipolar transistors as very robust ESD protection devices for automotive applications”, Proc. EOS/ESD Symp. 2003 , USA September 21-25, 2003 , Las Vegas, USA, pp. 313-318.

M. Blaho, M. Denison, V.Dubec, D.Pogany, M.Stecher, E.Gornik, Hot spot mapping in the DMOS devices for automotive applications, Tagungsband “Mikroelektronik Tagung” 2003″, Proc. Microelectronics days (of Austria), p. 329.

V. Dubec, S. Bychikhin, D. Pogany, E. Gornik, G. Groos, M. Stecher, “Error analysis in phase extraction in a 2D holographic imaging of semiconductor devices”, Proc. IS&T/SPIE 16th annual symposium on Electronic Imaging, Practical holography: Materials and Applications (EI03), San Jose, CA, USA, 2004, Proc. SPIE Vol. 5290, p. 233-242, Practical Holography XVIII: Materials and Applications; Tung H. Jeong, Hans I. Bjelkhagen; Eds.

S. Reggiani, E. Gnani, M. Rudan, G. Baccarani, S. Bychikhin, J. Kuzmik, D. Pogany, E. Gornik, M. Denison, N. Jensen, G. Groos, M. Stecher, “Predictive device simulation for ESD protection structures validated with transient interferometric thermal – mapping experiments”, Proc. ESSDERC’2005, Grenoble, Sept 12-16, 2005, [Eds. G. Ghibaudo, T. Skotnicki, S. Christoloveanu, M. Brillouet, ISBN0-7803-9203-5, IEEE Catalog number:05EX1087 ] p.411-414.

D. Pogany. S. Bychikhin, J. Kuzmik, E. Gornik, M. Denison, N. Jensen, M. Stecher, P. Rodin, G. Groos; “Observation of traveling current filaments in semiconductor devices using transient interferometric mapping”, Book of Abstracts: XXV Dynamics Days Europe, Berlin July 25-28, 2005, Europhysics Conference Series vol. 29E, p. 55-56, poster

Reggiani, S.; Gnani, E.; Rudan, M.; Baccarani, G.; Bychikhin, S.; Kuzmik, J.; Pogany, D.; Gornik, E.; Denison, M.; Jensen, N.; Groos, G.; Stecher, M.; “A new numerical and experimental analysis tool for ESD devices by means of the transient interferometric technique”; Electron Device Letters, IEEE; Volume 26, Issue 12,

Reggiani, S.; Gnani, E.; Rudan, M.; Baccarani, G.; Corvasce, C.; Barlini, D.; Ciappa, M.; Fichtner, W.; Denison, M.; Jensen, N.; Groos, G.; Stecher, M.; “Measurement and modeling of the electron impact-ionization coefficient in silicon up to very high temperatures”; Electron Devices, IEEE Transactions on; Volume 52, Issue 10, Oct. 2005 Page(s):2290 – 2299

Pogany, D.; Bychikhin, S.; Kuzmik, J.; Dubec, V.; Jensen, N.; Denison, M.; Groos, G.; Stecher, M.; Gornik, E.;”Thermal distribution during destructive pulses in ESD protection devices using a single-shot two-dimensional interferometric method”; Device and Materials Reliability, IEEE Transactions on Volume 3, Issue 4, Dec. 2003 Page(s):197 – 201

Pogany, D.; Dubec, V.; Bychikhin, S.; Furbock, C.; Litzenberger, M.; Naumov, S.; Groos, G.; Stecher, M.; Gornik, E.;”Single-shot nanosecond thermal imaging of semiconductor devices using absorption measurements”; Device and Materials Reliability, IEEE Transactions on; Volume 3, Issue 3, Sept. 2003 Page(s):85 – 88

Denison, M.; Blaho, M.; Rodin, P.; Dubec, V.; Pogany, D.; Silber, D.; Gornik, E.; Stecher, M.; “Moving current filaments in integrated DMOS transistors under short-duration current stress”; Electron Devices, IEEE Transactions on; Volume 51, Issue 10, Oct. 2004 Page(s):1695 – 1703

Denison, M.; Blaho, M.; Rodin, P.; Dubec, V.; Pogany, D.; Silber, D.; Gornik, E.; Stecher, M.; “Moving current filaments in integrated DMOS transistors under short-duration current stress”; Electron Devices, IEEE Transactions on; Volume 51, Issue 8, Aug. 2004 Page(s):1331 – 1339

Reggiani, S.; Gnani, E.; Rudan, M.; Baccarani, G.; Bychikhin, S.; Kuzmik, J.; Pogany, D.; Gornik, E.; Denison, M.; Jensen, N.; Groos, G.; Stecher, M.; “Predictive device simulation for ESD protection structures validated with transient interferometric thermal-mapping experiments”; Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European; 12-16 Sept. 2005 Page(s):411 – 414

Morgenstern, H.; Groos, G.; Kohne, H.; Stecher, M.; John, W.; Reichl, H.; “Algorithm for the automatic verification of complex mixed-signal ICs regarding ESD-stress”; Research in Microelectronics and Electronics, 2005 PhD; Volume 1, 25-28 July 2005 Page(s):213 – 216 vol.1

Pogany, D.; Bychikhin, S.; Gornik, E.; Denison, M.; Jensen, N.; Groos, G.; Stecher, M.; “Moving current filaments in ESD protection devices and their relation to electrical characteristics”; Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International; 30 March-4 April 2003 Page(s):241 – 248

D. Johnsson, W. Mamamnee, S. Bychikhin, D. Pogany, E. Gornik, M. Stecher; “Second Breakdown Behavior in Bipolar ESD Protection Devices During Low Current Long Duration Stress and its Relation to Moving Current-Tubes”; IRPS 2008;

D. Johnsson, M. Mayerhofer, J. Willemen, U. Glaser, D. Pogany, E. Gornik, and M. Stecher, “Avalanche Breakdown Delay in High Voltage PN-Junctions Caused by Pre-Pulse Voltage from IEC 61000-4-2 ESD Generators,” accepted for publication in IEEE T-DMR (2009).

S. Frei, W. Wu, U. Hilger, D. Johnsson, and M. Stecher, “Packaging- und Handling-Prufungen nach ISO 10605: Wie vergleichbar sind Prufungen mit unterschiedlichen ESD-Generatoren?” in proceedings of 10th Forum of the Interessengemeinschaft Electro Static Dischage e.V., Munich, 2007, pp. 89-97.

Reliability during Electro-Thermal Cycling

T. Smorodin, J. Wilde, M. Stecher: “Multiscale physics-of-failure for power technology metallization under fast temperature cycle stress”; Multiscale Materials Modeling, 544 – 546, 2006

T. Smorodin, J. Wilde, P. Alpern, M. Stecher: “Investigation and improvement of fast temperature-cycle reliability for DMOS-related conductor path design”; IEEE IRPS, 486 – 491, 2007

T. Smorodin, J. Wilde, M. Glavanovics, M. Stecher: “Power-cycling of DMOS-switches triggers thermo-mechanical failure mechanisms”; IEEE ESSDERC, 139 – 142, 2007

T. Smorodin, J. Wilde, M. Stecher: “Crack propagation in the interlayer dielectric of a power technology metallization under fast temperature cycle stress”, Micromaterials and Nanomaterials, 6, 232 – 233

J. Gaspar, T. Smorodin, M. Stecher, O. Paul: “Bulge testing of silicon nitride films at the wafer level”, Mikrosystemtechnik Kongress, 2007

Smorodin, T. Wilde, J. Alpern, P. Stecher, M.: A Temperature-Gradient-Induced Failure Mechanism in Metallization Under Fast Thermal Cycling Device and Materials Reliability, IEEE Transactions on; Sept. 2008; Volume: 8, Issue: 3; 590-599

Production Processes

M. Pölzl, M. Stecher; “A strategy to detect plasma damage process steps within a multilayer metallization technology”, 2nd International Symposium on Plasma Process-